An Innovative High-Performance Architecture for Vector and Matrix Math Algorithms

Intrinsity has designed an innovative embedded microprocessor for applications requiring very high performance, such as real-time signal processing tasks with large amounts of data. Traditionally, these applications have required hardware solutions such as ASICs, FPGAs, or DSPs. The Intrinsity FastMATHTM adaptive signal processorTM device, operates at 2 GHz clock speed and features an on-chip matrix co-processor for native matrix operations and single instruction, multiple data (SIMD) parallelization [1]. It is driven by a MIPS-basedTM scalar engine that issues instructions to the matrix unit and executes MIPS32TM instructions in parallel. It is programmable in C or other languages. These processors feature fixed-point math. A one Mbyte data-coherent on-chip L2 cache and two independent bidirectional one gigabit per second RapidIOTM ports enable data transmission to keep pace with the processor speed.